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lx1692 p roduction d ata s heet microsemi integrated products division 11861 western avenue, garden grove, ca. 92841, 714-898-8121, fax: 714-893-2570 page 1 copyright ? 2004 rev. 1.1, 2/9/2006 www. microsemi . com full bridge resonant ccfl controller tm ? description microsemi?s lx1692 is a cost reduced, third generation direct drive ccfl (cold cathode fluorescent lamp) controller. the integrated controller is optimized to drive ccfl?s using resonant full bridge inverter topology. resonant full bridge topology provides near sinusoidal waveforms over a wide supply voltage range in order to maximize the life of ccfl lamps, control emi emissions, and maximize efficiency. this new archi- tecture also provides a wide dimming range. the lx1692 includes safety features that limit the transformer secondary voltage and protect against fault conditions which include open lamp, broken lamp and short-circuit faults. the lx1692 regulates the ccfl brightness in three ways: analog dimming, digital dimming, or combined analog and digital dimming methods simultaneously to achieve the widest dimming range (> 60 to 1). the lx1692 can accept a brightness control signal that is either an analog voltage or a direct low frequency pwm. the lx1692 also features integrated gate drivers for the four external power mosfets. an integrated 4v ldo powers all internal control circuitry which greatly simplifies supply voltage requirements. the lx1692 is available in a 20-pin tssop and soic. important: for the most current data, consult microsemi ?s website: http://www.microsemi.com protected by u.s. patents: 5, 615,093; 5,923,129; 5,930,121; 6,198,234; patents pending product highlight part c_r i_r c_bst c_to brite_in ea_out isns d c b a dual fet dual fet v supply balancer lx1692 key features ? for wide voltage range inverter application (7v to 22v) ? patent resonant strike for unsurpassed striking power combined with best efficiency ? low stress to transformers ? excellent open circuit voltage regulation reduces transformer breakdown voltage requirements while striking higher voltage lamps ? one inverter for multiple panel types ? wide dimming range analog dimming: >3 to 1 digital dimming : >20 to 1 combined: >60 to 1 ? fool-proof striking ? programmable burst dimming frequency ? programmable time out protection ? fixed operating frequency ? open lamp voltage protection, short lamp protection, arc protection 1 benefits ? even display light distribution ? longer lamp life with optimized lamp current amplitude ? reduced operating voltage lowers corona discharge and prolongs module life ? high ?nits / watt? efficiency makes less heat and brighter displays applications ? lcd tv ? lcd monitor package order info pw plastic tssop 20-pin dw plastic soic 20-pin t a ( c) rohs compliant / pb-free rohs compliant / pb-free -20 to +85 LX1692IPW lx1692idw note: available in tape & reel. append the lett ers ?tr? to the part num ber. (i.e. LX1692IPW-tr) 1 arc protection is provided if the arci ng level is enough to be trigged. l l x x 1 1 6 6 9 9 2 2
lx1692 p roduction d ata s heet microsemi integrated products division 11861 western avenue, garden grove, ca. 92841, 714-898-8121, fax: 714-893-2570 page 2 copyright ? 2004 rev. 1.1, 2/9/2006 www. microsemi . com full bridge resonant ccfl controller tm ? absolute maximum ratings supply input volta ge(vddp) ............................................................................................. 6.6v vin_sns .........................................................-0.3v to (vddp+ 0.5v), not to exceed +6.6v digital input (ena ble) ................................... -0.3v to (vddp+0.5v) , not to exceed +6.6v analog inputs (isns, ov_sns, oc_sns)clamped to 14v max peak current 100ma analog inputs (brite_a, brite _d) ............. -0.3v to (vddp +0.5 v) , not to exceed +6.6v digital outputs ( aout, bout, cout, dout ) -0.3v to (vddp +0.5v) , not to exceed +6.6v analog outputs (i_r, icomp, vcomp)........ -0.3v to (vddp + 0.5v) , not to exceed +6.6v maximum operating junc tion temperat ure ..................................................................... 150c storage temperature range....................................................................................- 65 to 150c peak package solder reflow temp.(40 seconds max. expos ure) ......................... 260c(+0, -5) note: exceeding these ratings could cause damage to the device. all voltages are with respect to ground. currents are positive into, negative out of specified terminal . thermal data dw plastic soic 20-pin thermal resistance - junction to a mbient , ja 85 c/w pw plastic tssop 20-pin thermal resistance - junction to a mbient , ja 99 c/w junction temperature calculation: t j = t a + (p d x ja ). the ja numbers are guidelines for the thermal performan ce of the device/pc-board system. all of the above assume no ambient airflow. package pin out c_r i_r c_bst c_to vdda enable brite_d icomp vin_sns oc_sns ov_sns isns dout cout bout aout 1 10 11 20 vcomp brite_a gnd vddp pw p ackage (top view) 1 10 11 20 9 8 7 6 5 4 3 2 12 13 14 15 16 17 18 19 c_r i_r c_bst c_to vdda enable brite_d icomp vcomp brite_a vin_sns oc_sns ov_sns isns dout cout bout aout gnd vddp dw p ackage (top view) rohs / pb-free 100% matte tin lead finish functional pin description name description c_r lamp frequency programming capacitor pin ? lamp running frequency is set by the combination of c_r and i_r. the internal lamp current oscillator frequency can be forced to follow an external clock signal at this pin. in this case, the programmed frequency must be lower than the external frequency. minimum pulse width for external synch signal is 1sec. maximum duty is 50% i_r current reference resistor input. connects to an extern al resistor that determines the magnitude of internal bias currents. the i_r pin is a dc reference voltage of 1v. this voltage cannot be used for other than its intended function. the reference current established at th is pin by connecting an external resistor is used to charge a capacitor at the c_r pin. the nominal lamp fre quency can be adjusted by varying this resistor value in the range of 20k to 100k ohms. (note: c is in pf, r is in r _ i r _ c 3 lamp r c 10 242 f ? = other reference currents derived from i_r are used for the digital dimming burst oscillator and the strike time out function. p p a a c c k k a a g g e e d d a a t t a a
lx1692 p roduction d ata s heet microsemi integrated products division 11861 western avenue, garden grove, ca. 92841, 714-898-8121, fax: 714-893-2570 page 3 copyright ? 2004 rev. 1.1, 2/9/2006 www. microsemi . com full bridge resonant ccfl controller tm ? functional pin descri ption (continued) name description c_bst burst dimming mode frequency set capacitor. internal bias currents set via the i_r pin are scaled down and used to charge and discharge the capacitor connected at the c_bst pin. the voltage at the c_bst pin is a sawtooth waveform displaying a voltage that ranges from 0.5v to 2.5v. the frequency of the pwm for digital dimming is set by the i_r and c_bst pins. r _ i bst _ c dim r . c 98039 f = where r i_r is in and c c_bst is in nf, f dim is hz the internal burst oscillator frequency can also be forced to follow an external clock signal at this pin. in this case, the programmed frequency must be lower than the external frequency. c_to time out set capacitor. an external capacitor is charged with an on chip current source to create a voltage ramp. over voltage fault shutdown is disabled until c_to voltage rises above 3.5v, providing a user programmed strike interval. after c_to is reached to t he internal threshold level, then it will be discharged to 0v. also short lamp detection will be disabled until c_to voltage rises above 0.5v. strike interval time is to _ c r _ i c r 035 . 0 t ? = where r i_r is in to _ c r _ i c r 005 . 0 t ? = vdda analog voltage regulator output. this output pin is used to connect an external capacitor to stabilize and filter the on-chip ldo regulator. the input of the ldo is t he switched vddp supply. the ldo output is nominally 4.0v and is used to drive all circuitry except the out put buffers at aout, bout, cout and dout. the drop out voltage is typically 0.05v at 2ma; the average internal load. this output can supply up to a 5ma external load. the output capacitor should be a 100nf ceramic dielectric type. enable chip enable input. if logic high, all functions are enabled. if logic low, internal power is disconnected from the vddp pin, disabling all functions. logic threshold is 1.85v / 1.35v maximum over supply and temperature range. maximum current into vddp when enable < 0.8v, is 50a. enable may be connected directly to vddp if the disable function is not used brite_d brightness control input for digital dimming. the i nput signal can be a dc voltage or low frequency pwm signal. active dc voltage range is 0.5v to 2.5v. signa ls above 2.5v makes contin uous operation, voltages between 0.5v and 2.5v makes pwm digital dimming. digital dimming pulse width varies from 100% duty at 2.5v to 0% duty at 0.5v. a minimum brite_d input voltage (externally supplied) of approximately tbdv is required to prevent fault stop. pwm i nputs from either 3.3v or 5v logi c are permissible. frequency may range up to 1khz. max jitter of more than 1s / v on this input may cause noticeable lamp flicker. refer to dimming configuration table for setting. icomp error amp output for the lamp current regulator. this error amplifier is a gm type and does not require an external capacitor for stability. an external capacitor is connected from this pin to ground to adjust loop response of the inverter module. this capacitor value can vary from 0.1nf to 33nf as required by specific applications. error amplifier output vo ltage is not allowed to exceed t he peak voltage of its associated comparator ramp by more than 10%. vcomp voltage loop compensation pin for transformer output volta ge regulation. an external capacitor is connected from this pin to ground to adjust loop response. an extern al resistor divider is connected to limit the maximum output duty cycle while the ic is operating in strike mode. recommended resistor divider value are 100k from vdda and 300k to gnd. brite_a brightness control input for analog dimming. the input signal can be a dc voltage or a pwm signal that has been externally filtered to dc. active dc voltage range is 0 to 2v. signals above 2v and below 0.45v are clamped and do not change amplitude of output current. vin_sns input voltage sense pin. an external resistor and capa citor are connected to this pin to control slope of the frequency tracking oscillator and open lamp voltage regula tor timing ramp. ramp slope becomes steeper as the external bridge power supply increases provid ing rapid line voltage transient response. this feature permits using very low profile transformers that can easily saturate if simultaneously exposed to both high voltage and high duty cycle operation. p p a a c c k k a a g g e e d d a a t t a a
lx1692 p roduction d ata s heet microsemi integrated products division 11861 western avenue, garden grove, ca. 92841, 714-898-8121, fax: 714-893-2570 page 4 copyright ? 2004 rev. 1.1, 2/9/2006 www. microsemi . com full bridge resonant ccfl controller tm ? functional pin descri ption (continued) name description oc_sns over current sense input. the oc_sns input is compared to a 2v reference. the co mparator output shuts off the pwm outputs to prevent possible secondary failures. t he input voltage at this pi n is not rectified. normal operating voltage levels will be in the range of 0.5v to vddp. an abnormal voltage can operate continuously as high as 7v peak under load fault conditions. transients under fault conditions up to 11 v peak are permitted. an input voltage above 4 peak but less t han 11v peak may cause saturation but will not cause malfunction, phase reversal, or reliability issues with the ic. ov_sns over voltage sense input. this input pin monitors a voltage divider (approximately 1000:1) placed across the lamp. during strike mode the frequency tracking oscillat or uses the voltage waveform from the divider to determine and track load resonant frequency, and the open lamp voltage regulator uses it to regulate open circuit voltage. during both run and strike modes, f ault detection comparators monitor voltage amplitude to determine if load opens or shorts occur. see function al description section for details on internal circuit operation. frequency range of the input signal is from 30khz to 150khz and must not be rectified. normal operating voltage levels will be in the range of 0.5 to vddp peak, centered about +0.2 v dc . an abnormal voltage can operate continuously as high as 7v peak un der load fault conditions. transients under load fault conditions up to 11v peak are permitted. an input voltage above 4vpk may cause saturation, but will not cause malfunction, phase reversal, or reliability issues with the ic isns current sense input. the isns input is full wave rectif ied by an on-chip circuit, then presented to the inverting input of the current error amplifier. frequency range of the input signal is dc to 200khz. the isns pin also monitors lamp current to determine if t he lamp is ignited. if a single cycle at the isns pin is greater than 0.7v, the strike / run flip flop is clocked to the run state and threshol d of the strike comparator is lowered to 0.3v. during run mode current levels are continuously monito red to detect less than 0.3v. a counter clocked by rmpd_out is reset each time current is sensed at this in put. if the counter overflows (256 counts) a fault latch is set which shuts down the ic. this fault is expected to occur when the lamp is shorted to ground through an impedance of less than 2k ohms or the isns resistor itself is shorted. the counter is inhibited during digital dimming off time. normal operating voltage levels will be in the range of 0.5v to 5.5v. an abnormal voltage can operate continuously as high as 7v peak under load fault conditions. transient s under fault conditions up to 11 vpk are permitted. input voltages up 4v peak are li nearly rectified. an input voltage above 4v peak but less than 11v peak may cause saturation but wi ll not cause malfunction, phase reversal, or reliability issues with the ic. dout a buffer p-fet driver output. has a 20k pull up, r ds on nominal = p p a a c c k k a a g g e e d d a a t t a a
lx1692 p roduction d ata s heet microsemi integrated products division 11861 western avenue, garden grove, ca. 92841, 714-898-8121, fax: 714-893-2570 page 5 copyright ? 2004 rev. 1.1, 2/9/2006 www. microsemi . com full bridge resonant ccfl controller tm ? electrical characteristics unless otherwise specified, the following specifications apply over the operating ambient temperature -20 c t a 70 c except where otherwise noted and the following test conditions:. lx1692 parameter symbol test conditions min typ max units ` power power supply input voltage vddp 4.5 5.5 v power supply output voltage vdd_a vddp = 4.5v to 5.5v, i load = 5madc 3.8 4.0 4.2 v vddp operating current i bb c aout = c bout = c cout = c dout =2000pf, f lamp = 62.5khz 10 15 ma ` enable input enable logic threshold v th_en 1.6 1.85 2.0 v enable threshold hysteresis v h_en 500 mv enable high v en_high 2.4 vddp v enable low v en_low 0 0.8 v sleep mode current i dd_sleep v enable = 0v 20 50 a input resistance r enr 100 k ? ` under voltage lockout uvlo threshold vddp v th_uvlo_p rising edge 3.8 4.2 v uvlo hysteresis v h_uvlo 200 mv ` brightness control brite_a voltage range v r_br_a 0 vddp v full brightness brite_a input v br_full _a v r_br_d = vdda, t a =25 c 1.9 2 2.1 v full darkness brite_a input v dark_full_a v r_br_d = vdda 0 v full darkness brite_a input offset v darkfull_os v r_br_d = vdda, brite_a = 0v 0.35 0.45 0.55 v brite_d voltage range v r_br_d v r_br_a = vdda, t a = 25c 0.4 vddp v full brightness brite_d input v br_full _d v r_br_a = vdda 2.37 2.5 2.63 v full darkness brite_d input v dark_full_d v r_br_a = vdda 0.43 0.55 0.67 v ` burst ramp generator ramp valley voltage v rvv 0.43 0.55 0.67 v ramp peak voltage v rpv 2.37 2.5 2.63 v ramp frequency f ramp c_bst = 10nf, i_r = 40k 230 250 270 hz burst duty cycle range 0 100 % brite_d to dimpwm jitter j bdd c_bst = 10nf, brite_d = 2.4v 1 3 s burst pwm min duty resolution dr bst 1 % ` lamp frequency generator lamp frequency range f lamp 30 150 khz max lamp strike frequency f lamp_stk lamp is not ignited 150 khz lamp run ramp frequency f lamp_run lamp ignited, run mode, t a = 25 c, i_r = 40k, c_r = 100pf 60.6 62.5 64.4 khz lamp run ramp frequency regulation f lamp_reg 4.5 > vddp < 5.5v, t a = 25 c vddp = 5.5v 0.5 0.1 % / v %/ c ramp valley voltage vl rvv 0.2 v ramp peak voltage vl rpv 2.0 v ramp pwm jitter lfj 1 s ` vin_sns ramp ramp peak clamp voltage v rpcv vin = 8v, c_p = c_r = 100pf, r_p = tbd, vddp = 5v 5 vddp+0 .9 v vin_sns discharge current i vrvv 7 12.5 18 ma e e l l e e c c t t r r i i c c a a l l s s
lx1692 p roduction d ata s heet microsemi integrated products division 11861 western avenue, garden grove, ca. 92841, 714-898-8121, fax: 714-893-2570 page 6 copyright ? 2004 rev. 1.1, 2/9/2006 www. microsemi . com full bridge resonant ccfl controller tm ? electrical characteristics (continued) unless otherwise specified, the following specifications apply over the operating ambient temperature -20 c t a 70 c except where otherwise noted and the following test conditions:. lx1692 parameter symbol test conditions min typ max units ` bias block voltage at pin i_r v _ir i_r = 40k 1.0 v pin i_r max source current i max_ir 75 a ` striking block isns input strike threshold visns_stk 1.0 vpk min isns input threshold visnsmin 0.3 vpk lamp current regulation reference voltage during strike period v ref_stk 2 v number of zero crossing signal delay steps during strike n step 128 steps number of pulses zero crossing signal per step during strike n ps 8 pulses initial delay time t fdly 3.6 s last delay time t ldly after 128 steps 0.3 us ovsns zero comparator high v ovzh 0.843 v ovsns zero comparator low v ovzl -0.443 v ovsns peak comparator high v ovph 2.13 v ovsns peak comparator low v ovpl -1.73 v ` protection open lamp detection enable threshold v fen 3.5 v over voltage detection threshold v ovsth 3.2 v over current detection threshold v octh 2.0 v open lamp striking time out t stko 4.5v > vddp < 5.5v, isns = 0v, , c_to = 1f, i_r = 40k, vc_to > 3.5v 1.2 1.4 1.6 sec open lamp time out ( after ignition) t ol visns < 0.3v, vc_to >3.5v, lamp freq = 60khz 2.1 msec short lamp/over current detection enable threshold v dcod 4.5v > vddp < 5.5v, isns = 0v, c_to = 1f, i_r = 40k 0.7 v over current time out t oc voc_sns >2.0v, lamp freq = 60khz 500 sec short lamp time out (strike) t sl_stk vov_sns < 0.5v, visns < 1v 135 msec short lamp time out (run) t sl_run vov_sns < 0.5v, visns > 0.3v 500 sec over voltage time out t osl vov_sns > 3.2v, pulsed input 16 count e e l l e e c c t t r r i i c c a a l l s s
lx1692 p roduction d ata s heet microsemi integrated products division 11861 western avenue, garden grove, ca. 92841, 714-898-8121, fax: 714-893-2570 page 7 copyright ? 2004 rev. 1.1, 2/9/2006 www. microsemi . com full bridge resonant ccfl controller tm ? electrical characteristics (continued) unless otherwise specified, the following specifications apply over the operating ambient temperature -20 c t a 70 c except where otherwise noted and the following test conditions:. lx1692 parameter symbol test conditions min typ max units ` pwm block isns input voltage range v r_isns maximum recommended for linear operation of error amplifier -4 +4 vpk oc_sns input voltage range v r_oc -4 +4.0 vpk ov_sns input voltage range v r_ov -4 +4.0 vpk vin_sns input voltage range v r_vins -0.3 vddp vpk icomp error amp transconductance g m_eamp isns =1.5v 100 220 410 mho icomp output source current i s_eamp v_ eain = 1.0v 100 a icomp output sink current i sk_eamp v_ eain = 1.0v 100 a icomp output voltage range v r_eamp 0 vdda v isns-brite_a input offset voltage v os_eamp isns=1.5v, ta=25 c -100 0 100 mv icomp discharge current i d_icomp 10 ma icomp to a/b output propagation delay t d_comp 1100 ns vcomp high voltage v hi_vcomp vovsns = 0v, see note 1 vdda v vcomp sink current i lo_vcomp vvcomp = 2v 1.5 ma ` output buffer block output resistance r on_src vddp = 5v 30 ? output resistance r on_sink vddp = 5v 30 ? pull up resistance r up cout, dout 20 k pull down resistance r dn aout, bout 20 k output voltage high voh c aout = c bout = c cout = c dout =2000pf vddp-0.4 vddp v output voltage low vol c aout = c bout = c cout = c dout =2000pf 0 0.4 v min off time t off 320 ns note 1. external resistor divider is connected to vcomp pin. 100k between vdda and vcomp, 300k between vcomp to gnd. e e l l e e c c t t r r i i c c a a l l s s
lx1692 p roduction d ata s heet microsemi integrated products division 11861 western avenue, garden grove, ca. 92841, 714-898-8121, fax: 714-893-2570 page 8 copyright ? 2004 rev. 1.1, 2/9/2006 www. microsemi . com full bridge resonant ccfl controller tm ? simplified block diagram vdda ramp osc rmp_rst c_r + - 1v c_bst burst osc vdda vdda c_to vdda + - 3.5v brite_a + - vcomp + - 2v vin_sns + - enable sleep logic i_r vddp oc_sns fault detection & timer logic pwm block vddp vddp gnd aout bout cout dout + - isns fwr 1.0v/0.3v + - icomp 2.0v + - ov_sns 3.2v resonant timing detection & control logic brite_d output driver ldet 0.45v 2v 4v ldo vdda + - 0.5v c_bst c_bst vddp sleep sleep dim dim rmp_rst 1 0 sel out figure 1 ? block diagram b b l l o o c c k k d d i i a a g g r r a a m m
lx1692 p roduction d ata s heet microsemi integrated products division 11861 western avenue, garden grove, ca. 92841, 714-898-8121, fax: 714-893-2570 page 9 copyright ? 2004 rev. 1.1, 2/9/2006 www. microsemi . com full bridge resonant ccfl controller tm ? state diagram qc qa qd qb c1 t1 vin cout_p aout dout_p bout c1 t1 vin c1 t1 vin c1 t1 vin c1 t1 vin c1 t1 vin c1 t1 vin c1 t1 vin c1 t1 vin cout_p aout dout_p bout 012345678 0 1234 5 t0-t1 t1-t2 t2-t3 t3-t4 t4-t5 t5-t6 t6-t7 t7-t8 figure 2 ? state diagram b b l l o o c c k k d d i i a a g g r r a a m m
lx1692 p roduction d ata s heet microsemi integrated products division 11861 western avenue, garden grove, ca. 92841, 714-898-8121, fax: 714-893-2570 page 10 copyright ? 2004 rev. 1.1, 2/9/2006 www. microsemi . com full bridge resonant ccfl controller tm ? typical application part vdda c_r c5 0.1f c_bst c_to i_r enable brite_a vin_sns brite_d vcomp vddp aout bout gnd cout dout isns ovsns icomp oc_sns vdda c2 100pf c3 10nf c4 1f r1 40k vddp vdda r4 120k vin c9 100pf r9 100k r5 300k c7 10nf r3 47k r2 10k c8 1f c6 15nf c1 n/u cn1 c17 0.1f d1 5.1v vin r7 47k c10 10f g2p s2p g1n d2p s1n d1n g2p s2p g1n d2p s1n d1n c11 2.2f r8 47k c2 5.1v c16 0.1f t1 1:n c12 18pf 3kv c13 18nf c14 100nf r6 r cn2 con2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 16 17 18 19 20 lx1692 u1 u2 u3 figure 3 ? schematic a a p p p p l l i i c c a a t t i i o o n n s s
lx1692 p roduction d ata s heet microsemi integrated products division 11861 western avenue, garden grove, ca. 92841, 714-898-8121, fax: 714-893-2570 page 1 copyright ? 2004 rev. 1.1, 2/9/2006 www. microsemi . com full bridge resonant ccfl controller tm ? functional description o perating m odes two operating modes, strike and run, are employed by the lx1692. upon power up or enable going true, strike mode is entered. after a successful strike, e.g., lamp is ignited, run mode is entered. if ignition is unsuccessful, or if the lamp extinguishes while running, a fault is declared and the controller auto matically shuts down. o scillator c haracteristics the main oscillator in the lx1692 has two frequency control loops; a resonant tracking loop and a fixed frequency loop. the fixed frequency loop is user set via the i_r resistor and the c_r capacitor value. the resonant tracking loop follows the natural resonant frequency of the load. s triking the l amp lamp ignition is determined by monitoring the lamp current feedback volta ge at the isns pin. if less than 1.0v during the strike period, the lamp is considered not ignited and strike mode continues until ignition is detected or strike time out (approximately 1 - 2 seconds) is reached. if greater than 1.0v, strike is d eclared and a latch is set. the ic is now in ?run? mode. and threshold voltage for strike detect is reduced to 0.3v to permit a minimum 3:1 analog dimming ratio to be achieved. during strike, lamp operating frequency is always controlled by the resonant frequency tracking loop. at power up the lamp is not ignited and the loads? natural resonant frequency will be typically1.3 to 1.5 times higher than after the lamp has ignited. the tracking oscillator frequency will slew to near the natural resonant frequency of the load. at open circuit resonance load q is high and produces a large rise of voltage across the lamp, eliminating the need to use a high transformer turns ratio. additionally, since frequency is high, the volt-seconds applied to the transformer primary is minimized. this permits the use of smaller transformers that have reduced core cross sectional area. during striking operation, icomp is limited to 2.5v until ignition latch is set. when it starts the striking operation, it starts the striking frequency as user programmed operating frequency. and when ovsns is detected zero cross point , then tracking oscillator will start to sweep the frequency up to near to the circuit resonant frequency and it will track the frequency to reach user programmed open lamp voltage. at the moment of lamp ignition, operating frequency immediately switches to the pr ogrammed value of the fixed frequency oscillator. lamp current flow is sensed by the strike detection comparator, which decides to return pwm timing control to the fixed frequency oscillator f ault p rotection the lx1692 has shut down protection for all common lamp fault conditions. these include the following: a. open or broken lamp b. high voltage arcing on transformer secondary side c. short across lamp terminals d. short from high side of lamp to ground e. short from low side of lamp to ground ( current sense resistor shorted) three inputs from the lamp are monitored to detect these conditions, isns, ov_sns, and oc_sns. fault protection is designed to prevent fire or smoke from being generated by terminating inverter operation in the event of failures in the high voltage components and the power fet?s. all fault shut down events can only be reset by enable or vddp cycling. o pen l amp when the ic is first powered on or enabled, the inverter output voltage must be made higher than the normal operating voltage of the lamp to cause ignition. the lx1692 generates this higher ?strike? voltage by operating at the open circuit resonant frequency of the load inductance and capacitance. b ecause of its high unloaded q, a large resonant rise of voltage occurs across the lamp, and produces ignition. both resonant frequency and q of the lamp circuit are higher when the lamp is off than when on. the lamp may not ignite immediately when specified strike voltage is applied. it is customary to apply strike voltage for from 0.3 to 3 seconds to insure ignition of cold, dark, or aged lamps. the lx1692 has a programmable time out for this purpose. during strike time out, open lamp voltage is regulated to a value programmed by a voltage divider across the lamp and sensed at the ov_sns pin. d d e e s s c c r r i i p p t t i i o o n n
lx1692 p roduction d ata s heet microsemi integrated products division 11861 western avenue, garden grove, ca. 92841, 714-898-8121, fax: 714-893-2570 page 2 copyright ? 2004 rev. 1.1, 2/9/2006 www. microsemi . com full bridge resonant ccfl controller tm ? functional descript ion (continued) strike time out is programmed by selecting the capacitor value at the c_to pin. if the lamp has not ignited before the end of strike time out, a fa ult is declared and the ic outputs are latched off. h igh v oltage a rc or o ver p rogrammed v oltage if a high voltage arc occurs due to intermittent lamp contacts or component failure, if the over voltage feedback divider is improperly designed, or if the open lamp voltage regulation circuitry fails, the peak voltage on the ov_sns pin will rise above + 3.2 v dc . this creates a pulse that increments a 4 bit accumulating counter. after 16 events are counted, an open lamp fa ult is declared and the ic outputs are latched off. this fa ult is enabled at all times, including during lamp striking. the 4 bit counter is reset by signal c_bst which typically operates at 100 to 300 hz. also, ovsns pin voltage is greater than 3.2v, then icomp pin will be forced to discharge to 0v about 600ns. o pen l amp v oltage r egulation the open lamp voltage regulator regulates the peak voltage on the ov_sns pin to 1.97 volts, + the 0.2 volt offset, with a maximum tolerance 8% (158 mv). assuming an additional 5% tolerance for each of the two capacitors or resistors in the high voltage divider, maximum open lamp voltage tolerance at the system level is 18%. at the high side of tolerance, ov_sns peak voltage is +2.42v, on the low side of tolerance, ov_sns input voltage will be regulated at +1.914 v pk . if tighter total voltage regulation is needed in a given application, the feedback divider can be made with 1% resistors. i ntermittent or broken lamp after successful ignition after run mode is entered, an intermittent or open lamp problem can also be detected at the isns input. after ignition, peak voltage on the isns input is dependent on lamp current amplitude and voltage on the brite_a pin. i_sns signal amplitude should be designed to be greater than 400 mv pk (280 mv rms ) to insure a false open lamp fault shut down does not occur. a comparator monitors isns and generates a reset pulse to a watch dog timer for any peak voltage > 0.3v. the watch dog, a 9 bit binary counter, is reset once every cycle of i_sns voltage. if lamp current flowing through the isns resistor is too low (e.g., voltage is less than 0.3v peak), reset pulses are not generated and the counter is allowed to overflow and set the fault latch. nominal short circuit duration is 500 micro seconds when operating at 65khz. s hort circuits across the lamp terminals and shorts from the high voltage terminal to ground . soft shorts, including the ul safety test that places a 2k ohm resistor across the lamp connector, are normally not a problem because the current regulation circuitry limits current flow to the normal la mp amplitude. however, if the short is strong enough to lower the voltage at the ov_sns pin to less than 0.7 volts peak, the 7 bit shorted lamp time out counter reset is blocked. if this counter overflows a fault is declared and the ic outputs are latched off. this fault detection is enabled during both strike and run modes. this fault detection is disabled until voltage at c_to rises above 0.5v. the watch dog counter is not allowed to increment during digital dimming off time while in run mode. this fault will also be generated in the event of a hard short directly across the lamp terminals, or from the high voltage terminal to ground. s hort circuits from ground to the low side lamp terminal . a short to ground from the lamp return terminal also shorts out the lamp current sense resistor, removing current feedback to the controller. this short is detected as a rise in voltage across the oc_sns resistor which is located on the normally grounded side of the hv transformer secondary. a comparator se nses peak voltage > 2.0v dc at the oc_sns pin. this comparator clocks the 4 bit watch dog timer described above in the open lamp fault logic. sixteen events during a sing le cycle of the c_bst signal will overflow the watchdog counter and cause an over current shut down during either strike or run mode. o n chip ldo regulator output voltage is 4.0 5%. supplies all internal circuitry except output driver stage. capable to source 5ma to external circuitry. u nder voltage l ockout keeps chip outputs active off until vdda is high enough to insure stable operation. d imming m odes separate input pins are available for digital and analog dimming modes for maximum flexibility. see dimming truth table below. digital dimming rise and fall times can be controlled by the icomp capacitor (see dimming modes table). d d e e s s c c r r i i p p t t i i o o n n
lx1692 p roduction d ata s heet microsemi integrated products division 11861 western avenue, garden grove, ca. 92841, 714-898-8121, fax: 714-893-2570 page 3 copyright ? 2004 rev. 1.1, 2/9/2006 www. microsemi . com full bridge resonant ccfl controller tm ? dimming modes mode brite a brite d isns cbst i range dc voltage controlled analog 0 ? 2v vdda cap 3:1 dc voltage controlled reverse ana log vdda vdda 0?2v cap 1:3 external pwm controlled digital vdda pwm cap 60:1 dc voltage controlled digital vdda 0.5-2.5v cap 30:1 analog + voltage controlled digital 0 -2v 0.5-2.5v cap 60:1 a a p p p p l l i i c c a a t t i i o o n n s s
lx1692 p roduction d ata s heet microsemi integrated products division 11861 western avenue, garden grove, ca. 92841, 714-898-8121, fax: 714-893-2570 page 4 copyright ? 2004 rev. 1.1, 2/9/2006 www. microsemi . com full bridge resonant ccfl controller tm ? package dimensions pw 20-pin thin small shrink outline (tssop) c 1 2 3 e d e1 e a2 a1 a l b seating plane 1 m illimeters i nches dim min max min max a - 1.10 - 0.043 a1 0.05 0.15 0.002 0.006 a2 0.80 1.05 0.031 0.041 b 0.19 0.30 0.007 0.012 c 0.09 0.20 0.004 0.008 d 6.40 6.60 0.252 0.260 e 6.25 6.55 0.246 0.258 e1 4.30 4.50 0.169 0.177 e 0.65 bsc 0.026 bsc l 0.45 0.75 0.018 0.030 1 0 8 0 8 *lc - 0.10 - 0.004 dw 20-pin plastic (sowb) wide body soic p g c k l j d f b a m 110 11 20 seating plane *lead coplanarity note: 1. dimensions do not include mold flash or protrusions; these shall not exceed 0.155mm(.006?) on any side. lead dimension shall not include solder coverage. m illimeters i nches dim min max min max a 12.65 12.85 0.498 0.506 b 7.49 7.75 0.295 0.305 c 2.35 2.65 0.093 0.104 d 0.25 0.46 0.010 0.018 f 0.64 0.89 0.025 0.035 g 1.27 bsc 0.050 bsc j 0.23 0.32 0.009 0.013 k 0.10 0.30 0.004 0.012 l 8.13 8.64 0.320 0.340 m 0 8 0 8 p 10.26 10.65 0.404 0.419 *lc ? 0.10 ? 0.004 m m e e c c h h a a n n i i c c a a l l s s
lx1692 p roduction d ata s heet microsemi integrated products division 11861 western avenue, garden grove, ca. 92841, 714-898-8121, fax: 714-893-2570 page 5 copyright ? 2004 rev. 1.1, 2/9/2006 www. microsemi . com full bridge resonant ccfl controller tm ? notes production data ? information contained in this document is proprietary to microsemi and is current as of publication date. this document may not be modified in any way without the express written consent of microsemi. product processing does not necessarily include testing of all parameters. microsemi reserves the right to change the configuration and performance of the product and to discontinue product at any time. n n o o t t e e s s

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